The main problem when designing PCBs using any I2C device is that data and clock are always being transmitted and fed to the transceivers. This can lead to problems with radiation unless suitable precautions are taken. Coupling from the SCL and SDA lines can often occur where these lines are long tracks leading to the synthesiser.

The SCL and SDA lines pose particular problems as clock and Fig.3 Layout and decoupling of synthesiser supply pins DRIVE VEE RF RF VCC P0 CA RF INPUTS GND PLATED THROUGH GND OSCILLATOR CB=100n CA=100p CB data are always present on the I2C databus, regardless of whether the synthesiser is being addressed or not. These can couple into the synthesisier through any of the pins; it is therefore important to ensure that all pins are decoupled where possible. Unused ports should be taken to ground. Small decoupling capacitors may be placed directly on the pin to cut radiation into ports. P7 P6 P5 P0 P3 P4 SP5055S 100p 100p 112V Fig.1 Decoupling/grounding of used and unused ports I2C BUS LINE FILTERING I2C bus specifications permit a maximum of 400pF on the SDA andSCL lines. This figure refers to the maximum total capacitance present on the bus so therefore includes other devices. Most applications use a combination of 100pF decoupling capacitors on each line together with a series resistor of up to 100k , depending on the clock rate. SYNTHESISER DECOUPLING Supplies should be decoupled as close to the chip as possible. It is suggested that combination of 100pF and 100nF is used to give the best possible immunity against low and high frequency noise. Layout Care must be taken with layout to ensure that the supply rails are as short as possible and that no loops (either ground or supply) exist. If the layout permits, the VCC line should not be routed near the loop filter. Grounding The synthesiser should be taken to a clean ground separate from the track used to ground any of the oscillators. If possible, shielding should be introduced between the oscillators and the synthesiser to ensure that no spurious Fig.2 I2C bus line filtering coupling occurs. 100p 330 SP5055S SDA SCL 100p 330 TO MICROìíî AN168 TV/Satellite Synthesisers – Basic Design Guidelines Application Note AN168 – 2.4 June 1995 AN168 2 Phase Detector Gain (See Figure 7) The phase detector outputs pulses of current ICP μA with a pulse frequency equal to the comparison frequency and width proportional to the phase error. These pulses are averaged by the loop filter so that the phase detector gain is given by:- Kd = μA/radiation ….(1) Loop filter analysis (See Figure 8) The loop filter converts the current pulses from the charge pump into a voltage proportional to the phase error. The filter recommended for normal applications is shown in fig 8(c). The transfer characteristic is : F (S) = where T1 = C1 T2 = (C1+C2) R2 T3 = C2, R2 Procedure for design of filter Fig.8b shows an exact equivalent of the filter in figure 8(a). It is not possible to implement this configuration since the only points which are accessible are the input and output of the opamp, but it serves as a useful design model. If C2 and R1 are incorporated as a current “pulse integrator” into the phase detector then the remaining components consisting of the opamp, resistor [1 +C2/C1] R1 and capacitor C1 can be regarded as the loop filter. This procedure allows us to treat the filter as a 2nd order loop rather than the more complex 3rd order loop of figure 8(a). This loop will have a natural frequency of wO and damping factor z which we can select based on the application. The cut off frequency of the “pulse integrator” would normally be set to 5wO or more. By manipulation of the transfer function (see appendix) we can derive simple approximate design formulae for C1, R2 and C2. These are:- C1 = C2 = C1/5 R2 = Choice of Natural Frequency and Damping Factor When the synthesiser is reprogrammed, the application will usually require the VCO to settle to the new frequency within a specified time to a specified accuracy. Appendix 3 (Time Domain Response) shows that the time domain response to a frequency step is an exponentially decaying sinusoid. From this the natural frequency wO can be calculated if we specify the settling time tS and the accuracy we/ w, provided we already know the damping factor z. The damping factor must be chosen so that the system remains stable. For this the phase margin should be reasonably high say 0, > 45° or so. See Appendix 3 (Phase margin). The amount of ‘overshoot’ might also be used to estimate a value for z. See Figure 11. 2 z wO C1 VARACTOR LINE FILTERING Special care should be taken with the varactor line. A low pass filter may be placed in the varactor line to prevent ripple being fed along the line and mistuning the oscillator. A typical application is shown in Fig.4. Fig.4 Varactor line filtering The NPN transistor TR1, connected to the drive output, should be placed as close to the drive output pin as possible. The input to this transistor presents a very high impedance. Any length of track between the drive output of the synthesiser and the base of TR1 can act as an antenna which will feed unwanted signals into the transistor. To minimise this effect, a low value capacitor of, say 39pF may be connected between the base and collector of TR1 (as shown in Fig.5) without modifying the dominant loop characteristics. TO OSCILLATOR DRIVE OUTPUT 2N3904 10k 47k 10n Fig.5 Varactor drive transistor modification It is important that no other RF signals which may be present in the tuner, for example IF outputs, are routed anywhere near the synthesiser as they can also couple into the device. All of the above suggestions are made in an attempt to achieve the best possible phase noise and sideband performance for the synthesised oscillator. Whilst a good synthesiser application does not guarantee good phase noise performance, a bad synthesiser application will almost certainly limit the overall performance of the tuner and degrade phase noise compared to that of a free-running oscillator. CALCULATION OF LOOP COMPONENT VALUES Applications Circuit (See Figure 6) A typical synthesiser application circuit is shown in Figure 6. The optional additional filtering (referred to by Note 1 on this diagram) rolls off at a frequency well above the main loop filter. Its main purpose is to reduce any noise picked up on the varactor control line. Consequently its effect is ignored in this analysis. The following is a summary of the derivation of the basic design equations used to calculate the loop filter components. VARACTOR LINE DRIVE OUTPUT 39p win M Icp 2 (1+s T2) sT1 (1+sT3) KdKo PNwO 2 AN168 3 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 XTAL Q1 XTAL Q2 SDA SCL P7 P6 P5 330 330 100p 100p 4MHz 15p CH PUMP μP Note 3 100p P4 P3 P0 Note 7 100p 100p Note 6 2N3906 100p 100n Vcc 22k +12V Note 4 +5V RF IN 1n RF IN 1n Vee OUTPUT 39p 2N3904 10K 47K 10n Note 2 C2=39n 22K Note 1 Note 5 Note 8 +30V R1=22K VARACTOR LINE OSC OUT BAND INPUT AFC O/P C1=180n 1M 1 I2C P*N INTER FACE SP5055S TUNER Fig.6 Typical I2C Synthesiser application Note 1 : Varactor line filter reduces ripple. Note 2 : 39pF capacitor reduces radiation into NPN base. Note 3 : IIC bus filtering reduces transients. Note 4 : Decouple Vcc rail at both high and low frequencies. Note 5 : Choose appropriate loop filter components Note 6 : Decouple unused output ports Note 7 : Ground unused input ports Note 8 : When the varactor line disable (OS bit) is set, the 30V supply can be varied to directly control the analog voltage to the varactor. AN168 4 Fig.7 Phase detector current pulses Time ICP Fig.10 Frequency response of a high gain second order loop +6 +4 +2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 +8 0.1 0.2 0.3 0.4 0.5 0.7 1.0 2 3 4 5 7 10 PN M ( Frequency w wo z = 1.0 z = 2.0 z = 5.0 z = 0.3 z = 0.5 z = 0.707 6dB/octave A(w) )dB Fig.8 (b) Exact equivalent of Fig.8(a) R2 = R1 C2 C1 1 + C1 C2 R1 C2 and R1 incorporated into phase detector to allow simplified analysis. Fig.11 Time domain response to step in frequency 1.7 1.8 0 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 11 12 13 14 NORMALIZED OUTPUT FREQUENCY wt wo wout (t) Dwout 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.0 2.0 z = 0.1 Fig.8 (a) Phase detector and charge pump – third order type 2 loop Vout C1 R2 C2 Fin F (s) = Vout (s) / Fin (s) Fig.8 (c) Exact equivalent of Fig.8(a) (Practical alternative to Fig.8(a)) R2 = R1 C2 C1 1 + C1 R1 C2 Fig.9 System block diagram F(a) 1 P*N 1M 4MHz 7.8125kHz 670MHz Kd Ko s qout qin M = 512 = ref divider ratio P = 8 = prescaler divider ratio N = 10722 programmable divider ratio Kd = 150/(2x¹) μA/Rad = phase detector gain Ko = 20MHz/V = VCO gain AN168 5 we 1-z2 wout Example (Selection of wO and z) Assume the reprogramming causes a frequency step of 512 MHz and we wish the VCO to settle to an accuracy of 5.12 Hz within 100 mS. If the phase margin is 70° then the values for z and wO are:- z = tanØ = tan 70° = 0.8 2 (1+tan 2Ø) 2 (1+tan 270°) wn = — Ln = — Ln z ts 0.8 x 0.1 \wn = 237 rads/sec = 37Hz Design Formulae Using the known values of wo and z we have :- C1 = R2 = C2 = C1/5 5.12 1-0.82 512×106 Example (Selections of C1, C2 and R2) Suppose Kd = 150μA/2 μA/rad y, K O = 20 MHz/volt, P = 8, N = 10,722 whilst wO = 440 rads/sec and z = 0.87. \ C1 = = 180.16nF R2 = = 21.9K C2 = C1/5 = 36.12nF wO = 440 rads/sec = 70Hz. 150 x 10-6 x 20 x 106 x 2 8 x 10722 x 4402 x 2 2 x 0.87 440 x 180.6 x 10-9 KdKo PNwo 2 2z woC1 AN168 6 PHASE NOISE CONSIDERATIONS Noise Sources (See Figure 12) The noise present at the VCO output originates from three main sources. (a) Phase noise in the reference oscillator qr (b) Phase noise in the detector qd (c) Phase noise in the VCO qO. A small sinusoidal frequency modulation of the reference oscillator for example, with peak phase deviation of qr radius and modulation frequency wm would produce an output voltage of :- Vr(t) = V cos (wrt+qr sin wmt) = V cos (wrt)- Vqr cos [(wr+wm)t] – Vqr cos [(wr-wm)t] See Figure 13. Many such sidebands will be contributed by random noise modulation mechanisms in the reference oscillator such as thermal and schott noise. 2 2 Fig.12 System diagram including phase noise F(s) 1 P*N 1M qout qo qin qd qr VCO REF OSC Fig.13 Noise sidebands fr – fm fr + fm fr V Vqr Noise at Synthesiser Output The analysis of the System block diagram shows that the output noise spectrum is determined by :- qout (w) = A (w) qr (w) + MA (w) qd (w) + qO (w) Where A(w) is the system frequency response, described in Appendix 3 (system transfer charateristics) and shown in Figure 10. 1 – MA (w) PN PN M PN M PN M Noise inside the Loop Bandwidth The system frequency response inside the loop bandwidth is approximately given by :- A (w) = This is just a statement that the system output frequency is times bigger than the reference frequency. As a result the noise at the output is :- qout (w) = qr (w) + PN qd (w) INBAND Notice that the phase noise due to the phase detector is M times bigger than the phase noise from the reference oscillator. Thus the phase detector noise dominates. This noise appears as a plateau on the spectrum analyser display as shown in Figure 14. The inband VCO noise meanwhile has been suppressed by the loop filter. Thus the inband output noise is determined by the prescaler and programmable divider ratios and by the noise floor of the detector. qoutINBAND = PN qd (w) Noise outside the Loop Bandwidth The output noise outside the loop bandwidth is approximately given by :- qoutOUTBAND = qO (w) This shows that any noise components due to the VCO having frequencies outside the loop bandwidth are not suppressed. Thus the phase noise outside of the loop bandwidth is determined largely by the performance of the VCO itself and no improvement of this can be gained by the use of the synthesiser. See Figure 14. Example (Low Comparison Frequency Synthesiser) A synthesiser such as the SP5510 operates with a comparison frequency of 7.8125 KHz. If an LO of 512 MHz is to be synthesised then :- PN = = 65536 fout Synthesized VCO Unsynthesized VCO Noise Floor Fig.14 Output spectrum 512 x 106 7.8125 x 103 AN168 7 In practice, since the phase detector noise floor predominates, the reference oscillator noise may be ignored. If the phase detector noise floor is -130 dBc then the noise floor at the output is given by :- qout = -130dBc + 20 log 65536 = -130 + 96.3 = -33.7dBC Example (High Comparison Frequency Synthesiser) The SP5058 has been designed to operate, with a high comparison frequency, typically 250 KHz. If an LO of 2.048 GHz is to be synthesised then :- PN = = 8192 If the phase detector noise floor is -140 dBc then the noise floor of the output is :- qout = -140dBc + 20 log 8192 = -140 + 78.3 = -61.7dBC High comparison frequency synthesisers are used in applications where the phase noise within the loop bandwidth is an important consideration such as scrambled satellite or cable systems using the double conversion principle. See Figure 15 (shown below). 2.048 x 109 250 x 103 Fig.15 Example of double conversion from VHF/UHF frequencies to TV IF SP5058 SP5022 1650-2500MHz 50-900MHz 38.9MHz 1.6GHz AN168 8 APPENDIX 1 (NOTATION) Description of symbols used. qout(s) = VCO output phase qin(s) = Reference oscillator phase wout(s) = VCO output frequency win(s) = Reference oscillator frequency KO = VCO gain in rads/sec/volt Kd = Phase detector gain = Amps/rad M = Reference divider ratio P = Prescaler divider ratio N = Programmable divider ratio wO = Natural frequency of 2nd order system in rads/sec z = Damping factor of 2nd order system S = Laplace frequency variable S =S/wO = Normalised laplace frequency variable w = w/wO = Normalised frequency APPENDIX 2 (SYSTEM EQUATIONS) System Transfer Characteristics (See Figure 9) G (s) = qout (s) = wout (s) = KOKd (s) / Ms qin (s) win (s) 1 + KOKd (s) / PNs Open Loop Gain GOL (s) = KoKd F (s) / PNs USE OF VARACTOR LINE DISABLE (OS BIT) IN TUNER ALIGNMENT In tuner manufacture, many of the wound components must be aligned to give the desired tilt factors, filter matching and correcting range for local oscillators and IF output. This is a time-consuming process and is usually carried out by tuning the synthesiser to a number of different channels and aligning to these points (shown l on Fig.17). Each time a new channel is selected, data must first be written to the synthesiser. In this example, 6 sets of data must be sent from the micro to the synthesiser. However, if the varactor line disable bit OS is used, the varactor line voltage can be externally controlled. This allows the selected channels to be tuned without the use of a micro to address and program the device. The varactor line disable facility is available on all Mitel I2C bus synthesisers and also on I2C bus compatible 3-wire synthesisers such as the SP5024 and SP5054. With the latter devices, the varactor drive is disabled by applying a negative voltage to the ENABLE pin (pin 10) and sourcing greater than 350μA from the device. using this method of tuning can result in appreciable saving of test time. 38.9MHz Fig.16 Alignment of IF output Fig.17 Varactor tuning curve VARACTOR VOLTAGE CHANNEL CHARGE PUMP 1 2 3 18 17 16 OS EXTERNAL ALIGNMENT VOLTAGE 130V Fig.18 Application of external tuning voltage Icp 2 AN168 9 APPENDIX 3 (2ND ORDER TYPE 2 SYSTEM) System Transfer Characteristics G (s) = 1 + 2 s s2 + 2 z s + 1 Where:- Normalised Laplace variable is s = s/wo Natural Frequency is wo= KdKo PNT1 Damping Factor is z = woT2/2 T1 = C1 T2 = 1 + C2 R1C1 C1 System Frequency Response (See Figure 11) Amplitude Phase A(w) = 1+(2zw)2 , Ø(w)=atan(2zw)-atan (1-w2)+(zw)2 Time Domain Response (See Figure 12) wout (t) = wout 1 – e (cos 1-z2 wn – z sin 1-z wn) 1 – z2 1 – z2 wout (t) = output frequency at time t. wout = output frequency step caused by reprogramming the divider Settling Time ts = – Ln 1 – z2 wnz Where we = wout – wout (ts) radians/sec is the error in the output frequency at time ts following a step adjustment of the output frequency of w. PN M Open Loop Gain GOL (s) = 1 + 2z s s2 Open Loop Frequency Responses amplitude AOL (w) = 1 + 2z w2 Where w = w w2 w0 phase ØOL (w) = – + atan (2zw) Phase Margin Ø1 = atan (2zw) where unity gain frequency w1 = 2z2 + 4z4+1 \z = tanØ1 2 (1+tanØ 1) we wout zw 1-w2 ( ) -zwnt