S-Band Low Noise Amplifier Using the ATF-10136

This application note documents the results of using the ATF-10136 in low noise amplifier applications at S band. The ATF-10136 device is capable of a 0.5 dB noise figure at 2.3 GHz. The ATF-10136 is packaged in a low cost 100 mil micro-x package.

To achieve the lowest possible noise figure that the device is capable of producing, the input matching structure must transform the system impedance, usually 50 ohms, to an impedance represented by GO. GO is the source reflection coefficient that must be presented to the device for it to yield the rated noise figure. This is in contrast to presenting to the device the complex conjugate of S11 which will match the device for maximum gain and minimum input VSWR. Plotting GO versus frequency for the ATF-10136 and interpolating the data for a frequency of 2.3 GHz reveals a reflection coefficient of 0.65 @ 59 degrees. This is plotted on the Smith Chart shown in Figure 1 as Point B. One matching solution is to use a series quarterwave transmission line to match the real part and a reactive component to match the imaginary part of the reflection coefficient. A quarterwave transmission line of the appropriate characteristic impedance Zo will match two impedances over a narrow bandwidth. The following is the formula for calculating the required characteristic impedance: A transmission line of characteristic impedance of 44 ohms transforms the 50 ohm source impedance to 39 ohms. This is plotted as Point A on Figure 1. At this point, it is still the resistive axis. A series inductor with an inductive reactance of 74 ohms then transforms the impedance at Point A to GO at Point B. 74 ohms of inductive reactance is equivalent to a series inductance of 5 nH at 2.3 GHz (Z = jwL). An inductor of this size is often difficult to build; and more difficult to tune during the initial breadboard stage of design. Quite conveniently, Zo = Z1 x Z2 PT.B PT.A Zo GO Figure 1. Smith Chart Shows Input Match 2 a series inductive reactance can be simulated by an equivalent shunt capacitive reactance when it is physically spaced a quarter wavelength away on the transmission line. Using the Smith Chart, it can be shown that the equivalent shunt component can be calculated from the following formula: For a 5 nH inductor, Xc calculates to be 26.2 ohms or 2.6 pF at 2.3 GHz. Shown in Figure 2 are the resultant input matching networks. The LNA design will be based on the network with the shunt capacitive element. Since the input is terminated in GO and not 50 ohms, the output of the FET must be matched to GL = S22′. This accounts for the imperfect isolation through the FET. GL is given by: Substituting in the parameters for the ATF-10136 at 2.3 GHz: S11 = 0.75 @ -74 degrees S22 = 0.29 @ -34 degrees S12 = 0.09 @ 55 degrees S21 = 4.5 @ 105 degrees GO = 0.65 @ 59 degrees Yields GL = 0.39 @ 115 degrees Note: The output reflection coefficient has been significantly transformed due to the change in generator impedance presented to the device. A Smith Chart exercise similar to that used to generate the input network yields the circuits shown in Figure 3 for the output network. Computer Optimization The initial design can be performed quite easily with a basic understanding of the Smith Chart. It provides a basis with which to begin optimization. With the help of a computer, modeling and optimizing the basic matching networks for a desired performance is attainable. One of the main advantages of a computer optimization program is the ability to model the electrical effects associated with the actual circuit realization of the LNA. Examples include the discontinuity associated with soldering the 0.020 inch wide lead down to a piece of etch that is significantly wider; the effect of several lines intersecting at one point; the effect of adding plated through-holes to ground the source leads. These small yet often significant discontinuities are often tedious to model on the Smith Chart, but are a trivial matter for the computer. The simulation software is especially useful when modeling source inductance on the GaAs FET and making Xc = XI -Zo2 GL = S22 + S12 x S21 x GO 1 – S11 x GO 5 nH 2.6 pF l/4 Zo = 44 W l/4 Zo = 44 W SERIES INDUCTOR APPROACH SHUNT CAPACITOR APPROACH Figure 2. Input Matching Networks 1.7 nH 1.2 pF l/4 Zo = 37 W l/4 Zo = 37 W SERIES INDUCTOR APPROACH SHUNT CAPACITOR APPROACH Figure 3. Output Matching Networks 3 tradeoffs between noise figure, gain, input VSWR and stability. Although an LNA design may be unconditionally stable at the operating frequency, there will be no guarantee that the LNA will not oscillate at some other frequency unless a stability analysis is performed. The analysis should be performed at all frequencies over which the device has gain. An out-of-band oscillation could possibly be at a large enough amplitude to cause a reduction in in-band gain or an increase in noise figure. Although it is not necessary that an LNA be unconditionally stable at all frequencies, stability should be analyzed so that the areas of potential instability can be evaluated and problem source and load impedances can be avoided. The revised circuit after optimization is shown in Figure 4. The input matching network consists of microstriplines Z1 and Z2. It was later found empirically and confirmed on the computer that adding an additional stub Z3 reduces the noise figure slightly. The blocking capacitors were chosen to be 10 pF to offer some low frequency rejection. Quarterwave lines are utilized for bias decoupling. 50 ohm chip resistors are used for low frequency resistive loading and ensure stability at low frequencies. Both 1000 pF and 0.1 mF capacitors provide a low impedance path to ground for the 50 ohm chip resistors. It was also determined with the help of the computer that using a quarterwave open circuited low impedance line in the gate bias decoupling circuit as opposed to using a bypass capacitor also improved stability near the band of operation. Figure 4. 2.3 GHz LNA Schematic Z3 Z2 Z5 INPUT 10 50 50 1000 0.1 Z1 Z4 50 W 10 K R1 10 K LL 10 OUTPUT 10 1000 0.1 10 mF 10 mF 2N2907 DC – DC INVERTER – + R3 R2 REGULATOR 5 V VCC 50 W 4 An often overlooked topic is effective grounding and proper modeling of the FET source leads. Both the S parameters and Noise parameters of the device are characterized in fixtures that provide a near perfect ground at both source leads. In actual circuits, it is usually impossible to ground the sources right at the package. The situation is further compounded if self biasing is used and the source leads are bypassed to ground with capacitors. Generally the source leads are laid down on a path of etch and only reach the bottom side groundplane via plated through holes. The effect of this source inductance can be easily analyzed with the computer. The seemingly small source leads and vias do add a significant amount of inductance to the circuit. Fortunately some amount of inductance actually helps to minimize input VSWR when the device is purposely mismatched for low noise operation. Consult Reference 1 for additional information on the effect of source inductance on LNA operation. It is strongly suggested that all source leads be DC grounded for best overall performance above 2 GHz. The source leads are modeled as microstriplines 0.020 inches wide (the width of the source lead). The most dominant effect of adding source inductance is that input VSWR is improved significantly. In the common source configuration, inductance in series with the source adds negative feedback which has the effect of increasing the real part of the device input impedance. The end result is that GO and S11* now occur more closely together on the Smith Chart making a simultaneous noise and gain match a little easier to obtain. Source feedback also has the effect of taking a device that is not unconditionally stable and making the circuit it is used in stable at the frequency of operation. Generally, as source inductance is increased, stability at and below the frequency of operation is improved. Adding an excessive amount of inductance tends to make the amplifier unstable at frequencies higher than the normal operating frequency. There exists an optimum amount of source inductance for a particular device and circuit topology. For the ATF-10136 at 2.3 GHz the optimum source leadlength is approximately 0.060 inches. Bias Circuitry The preferred technique for biasing LNAs is using active biasing versus passive biasing. Active biasing offers the advantage that device-todevice variations in pinchoff voltage and Idss don’t necessitate a change in source resistor value for a given bias condition. The active bias network automatically sets Vgs for the desired drain voltage and drain current. The typical active biasing scheme for FETs requires that the source leads be grounded and an additional supply used to generate the negative voltage required at the gate for typical operation. Directly grounding the FET source leads has the additional advantage of not requiring bypass capacitors to bypass a source resistor that would typically be used for self biasing in a single supply circuit. The parasitic inductance associated with the bypass capacitors often creates stability problems either inband or at higher frequencies. 5 The negative voltage can be supplied from a DC-DC converter driven by the same voltage regulator that feeds the active bias network. A DCDC converter circuit can be built around a standard NE555 timer device. A suitable circuit is described in detail in Hewlett-Packard Application Note AN-A002. A simpler approach is to use one of the newer integrated DC-DC converters. The Teledyne Semiconductor TSC7662A used in the active bias circuit shown in Figure 4 has been used successfully in many circuits. The drain voltage is determined by resistors R2 and R3 shown in Figure 4. Resistor R1 sets the drain current. The typical bias point for low noise operation for the ATF-10136 is shown in Table 1. Suggested resistor values for the active bias networks are also shown. Performance Typical LNA performance for the ATF-10136 LNA is shown in Table 2. Measured performance of several LNAs as compared to the computer simulation is within a tenth of a dB on noise figure and within a dB on gain. ATF-10136 Noise Figure Gain Actual 0.60 dB 13.5 dB Simulation 0.54 dB 14.4 dB Table 2. Device Vds Id R1 R2 R3 ATF-10136 2.0 V 25 mA 70 1200 1000 Table 1. 6 Figure 5. 1X Artwork The artwork shown in Figure 5 is designed for material with a dielectric constant of 2.2 and a thickness of 0.031 inch. Suggested material includes Duroid™ 5880 or Taconics TLY-5. The Touchstone™ computer simulation for the ATF-10136 LNA is contained in Tables 3 and 4. Reference: 1. A. Ward, “Low-Noise VHF and L-Band GaAsFET Amplifiers”, RF Design, Feb. 1989. ® All registered trademarks and trademarks remain the property of their respective companies. 7 Figure 6. TouchstoneTM Circuit Configuration